The present disclosure generally relates to a binary module optimizing technique, and more particularly relates to a technique for testing an optimized binary module.
In recent years, binary module optimizing technologies have garnered attention along with the updating and downsizing of hardware. Binary module optimizing technologies are the technologies used to optimize compiled binary modules that are legacy assets (for example, binary modules in COBOL programs) to create binary modules for new machines without having to recompile the source code.
International Business Machines Corporation has released the IBM (registered trademark) COBOL Binary Optimizer from IBM alphaWorks which is software for optimizing binary modules (hereinafter referred to simply as “binary optimization”). The IBM COBOL Binary Optimizer optimizes binary modules in COBOL programs (that is, the original binary modules) without having to recompile the source code by using the new z/Architecture instructions available in systems that execute optimized binary modules.
Patent Literature 1 describes that a program is divided into sections at irrecoverable points such as system calls in the original program to be executed and at thread synchronization points, this process is performed by the compiler, and by dividing a program at a thread synchronization point, execution results from the two threads are guaranteed to be identical provided the program have performed the appropriate synchronization and transient faults have not occurred.
Patent Literature 2 describes that a dynamic binary rewriter (DBR) service aggregates samples from a hardware performance monitor, selects regions by estimating the program structure around hot samples, performs modifications (for example, optimization) on the selected regions, and generates replacement code.
Patent Literature 3 describes an automated system for generating optimized code from source code provided by a user for use in applications in a certain field on a certain hardware platform including at least one processor, which is equipped with an analyzing device enabling the system to create optimization rules from tests using benchmark sequence, static parameters, and dynamic parameters, and performance measurements.
Patent Literature 4 describes a program transport supporting program for supporting efficient program transport operations, which analyzes programs to be transported using a static analyzer for identifying, by static program analysis, code portions that are not affected by the transport, and a dynamic analyzer for identifying code portions that are not affected by the transport with regard to existing test data Ti regardless of the operating conditions on the basis of information collected using execution traces of the program using the test data. A program converter inserts into the original program a function for collecting runtime information in code portions which may be affected by the transport before tracing the execution of the program.
Patent Literature 5 describes a program code converter which is able to reflect, in the destination binary code, optimizations in the source binary code when program code is converted for use by a different processor.
Non-Patent Literature 1 describes a software approach to transient fault detection for multicore architectures in which the same program is executed in parallel and synchronized at checkpoints in response to the detection of a transient fault. The output is compared, and redundant execution duplicating the results is used (see “4.10 Transient Fault Recovery” in the right-hand column on page 7).
Non-Patent Literature 2 describes a test system for the Java (registered trademark) JIT Compiler, in which a random test program is generated, and the execution results of the program on reliable Java Runtime are compared to execution results on the program which is compiled by the JIT compiler that is being tested (see the abstract in the left-hand column of page 1).